HYB25D256400BT Datasheet, PDF (19/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank
must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and
BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row
to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued
to that row, subject to the t_RCD specification. A subsequent Active command to a different row in the same
bank can only be issued after the previous active row has been “closed” (precharged). The minimum time
interval between successive Active commands to the same bank is defined by t_RC. A subsequent Active com-
mand to another bank can be issued while the first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval between successive Active commands to different
banks is defined by t_RRD.
Activating a Specific Row in a Specific Bank
CK
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
HIGH
RA
BA
RA = row address.
BA = bank address.
Don’t Care
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2003-01-09, V1.1