HYB25D256400BT Datasheet, PDF (8/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Block Diagram (16Mb x 16)
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
13
A0-A11,
BA0, BA1
15
2
2
9
Column-Address
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 256x 32)
Sense Amplifiers
I/O Gating
DM Mask Logic
256
(x32)
Column
Decoder
8
COL0
1
32
32
32
Data
16
16
16
DQS
1
Generator
COL0 _Input
DQS
Register
Write ^{Mask 1}
FIFO
&
Drivers
1
2
32 ¹⁶
1
1
1
16
16
clk clk
16
16
out in _Data
CK,
COL0
CK
2
DQ0-DQ15,
DM
LDQS, UDQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the
load of the bidirectional DQ , UDQS and LDQS signals.
Page 8 of 77
2003-01-09, V1.1