HYB25D256400BT Datasheet, PDF (61/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C £ T_A £ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V) (Part 2 of 2)
Symbol
Parameter
t_RPRE Read preamble
t_RPST Read postamble
t_RAS Active to Precharge command
t_RC
Active to Active/Auto-refresh command
period
DDR200
-8
Min
Max
0.9
1.1
0.40
0.60
50 120,000
DDR266A
-7
Min
Max
0.9
1.1
0.40
0.60
45 120,000
DDR266
-7F
Min
Max
0.9
1.1
0.40
0.60
45 120,000
70
65
60
t_RFC
Auto-refresh to Active/Auto-refresh com-
mand period
80
75
75
t_RCD Active to Read or Write delay
20
t_RP Precharge command period
20
t_RAP Active to Autoprecharge delay
20
t_RRD Active bank A to Active bank B command
15
t_WR Write recovery time
15
t_DAL
Auto precharge write recovery
+ precharge time
20
15
20
15
20
20
15
15
15
15
(twr/tck) + (trp/tck)
t_WTR Internal write to read command delay
1
1
1
t_XSNR Exit self-refresh to non-read command
80
75
75
t_XSRD Exit self-refresh to read command
200
200
200
Average Periodic Refresh Interval (8192
t_REFI refresh commands per 64ms refresh
period)
7.8
7.8
7.8
DDR333
-6
Min
Max
Unit Notes
0.9
1.1 t_CK 1-4
0.40
0.60 t_CK 1-4
42 70,000 ns 1-4
60
ns 1-4
72
ns 1-4
18
ns 1-4
18
ns 1-4
18
ns 1-4
12
ns 1-4
15
ns 1-4
t_CK 1-4,9
1
t_CK 1-4
75
ns 1-4
200
t_CK 1-4
7.8 ms 1-4, 8
1. Input slew rate >= 1V/ns for DDR266 & DDR333 and = 1V/ns for DDR 200
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other
than CK/CK, is V_REF. CK/CK slew rate are >= 1.0 V/ns
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage
level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance
(bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS
will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at
this time, depending on t_DQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarilty tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between
VOH(ac) and VOL(ac)
Page 61 of 77
2003-01-09, V1.1