HYB25D256400BT Datasheet, PDF (57/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
IDD Specification and Conditions
(0 °C £ T_A £ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V)
Symbol Parameter/Condition
IDD0
Operating Current: one bank; active / precharge; tRC = tRC MIN;
DQ, DM, and DQS inputs changing once per clock cycle; address
and control inputs changing once every two clock cycles
x4/x8
x16
IDD1
Operating Current: one bank; active/read/precharge;
burst length 4;
Refer to the following page for detailed test conditions.
x4/x8
x16
DDR200
DDR266A
DDR266
DDR333
-8
-7
-7F
-6
Unit
typ. max. typ. max. typ. max. typ. max.
70 90 75 100 83 110 85 110
mA
72 95 77 105 86 115 88 115
mA
80 100 90 110 98 120 100 120
mA
83 105 94 115 102 125 104 125
mA
Precharge Power-Down Standby Current: all banks idle; power-down mode;
IDD2P _{CKE <= VIL MAX}
5
7
6
8
6
8
6
9
mA
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
IDD2F CKE >= VIH MIN; address and other control inputs changing once per clock cycle, VIN 30 35 35 40 35 40 45 55
mA
= VREF for DQ, DQS and DM.
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
IDD2Q CKE >= VIH MIN; address and other control inputs stable
at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
18 22 20 25 20 25 25 28
mA
Active Power-Down Standby Current: one bank active; power-down mode;
IDD3P _{CKE <= VIL MAX; VIN = VREF for DQ, DQS and DM.}
Active Standby Current: one bank active; CS >= VIH MIN;
IDD3N ^{CKE >= VIH MIN; tRC = tRAS MAX; DQ, DM, and DQS inputs}
changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: one bank active; BL2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of
IDD4R _{data outputs changing on every clock edge; CL2 for DDR200 and}
DDR266(A), CL3 for DDR333 and DDR400; IOUT = 0mA
Operating Current: one bank active; Burst = 2; writes; continuous
IDD4W
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL2 for
DDR200 and DDR266(A), CL3 for DDR333 and DDR400
x4/x8
x16
x4/x8
x16
x4/x8
x16
13 16 15 18 15 18 18 21
mA
40 45 50 55 50 55 60 65
mA
42 50 52 60 52 60 63 70
mA
79 95 95 115 95 115 110 140
mA
89 110 107 130 107 130 124 160
mA
85 105 105 125 105 125 125 145
mA
96 120 119 140 119 140 141 165
mA
IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
126 170 135 180 135 180 144 190
mA
Notes
4
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on
standard version 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5
mA
low power version 1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25 mA
IDD7
Operating Current: four bank; four bank interleaving with burst
length 4;
Refer to the following page for detailed test conditions.
x4/x8
x16
150 210 171 225 171 225 208 270
mA
158 220 180 235 180 235 218 285
1. IDD specifications are tested after the device is properly initialized and measured
at 100 MHz for DDR200, 133 MHz for DDR266(A) and 166 MHz for DDR333
2. Input slew rate = 1V/ns.
3. Enables on-chip refresh and address counters
4. Test condition for typical values : VDD = 2.5V ,Ta = 25°C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10°C
1, 2, 3
1, 2
Page 57 of 77
2003-01-09, V1.1