HYB25D256400BT Datasheet, PDF (27/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
CK
CK
Command
Address
DQS
DQ
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2
Read
BAa, COL n
NOP
CL=2
BST
NOP
NOP
NOP
DOa-n
No further output data after this point.
DQS tristated.
CAS Latency = 2.5
Read
BAa, COL n
NOP
BST
NOP
NOP
NOP
CL=2.5
DOa-n
No further output data after this point.
DQS tristated.
DO a-n = data out from bank a, column n.
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Don’t Care
Page 27 of 77
2003-01-09, V1.1