HYB25D256400BT Datasheet, PDF (29/77 Pages) Infineon Technologies AG – 256-Mbit Double Data Rate SDRAM, Die Rev. B

HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2
Read
NOP
BA a, COL n
CL=2
PRE
BA a or all
NOP
NOP
t_RP
DOa-n
ACT
BA a, ROW
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2.5
Read
BA a, COL n
NOP
PRE
BA a or all
CL=2.5
NOP
NOP
t_RP
DOa-n
ACT
BA a, ROW
DO a-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Don’t Care
Page 29 of 77
2003-01-09, V1.1