HYB25D256161CE Datasheet, PDF (9/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Overview
Read and write accesses to the DDR SGRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are used to select the bank and the starting column location
for the burst access.
The DDR SGRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SGRAMs allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 2 Ordering Information
Part Number¹⁾
HYB25D256161CE–4
HYB25D256161CE–5
Organisation
×16
1) HYB: designator for memory components
25D: DDR SGRAMs at V_DDQ = 2.5 V / 2.6 V
256: 256-Mbit density
C: Die revision C
Clock (MHz)
250
200
Package
P-TSOPII-66-1
Datasheet
9
Rev.1.0, 2004-02