HYB25D256161CE Datasheet, PDF (34/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

CK
CK
Command
Address
DQS
DQ
DM
HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BAa, COL b
t_DQSS (max)
DIa- b
NOP
Read
NOP
t_WTR
BAa, COL n
CL = 3
1
1
CK
CK
Command
Address
DQS
DQ
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BAa, COL b
t_DQSS (min)
DI a-b
NOP
Read
NOP
t_WTR
BAa, COL n
CL = 3
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
t_WTR is referenced from the first positive CK edge after the last data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
Figure 19 Write to Read: Interrupting (CAS Latency = 3; Burst Length = 8)
Don’t Care
Datasheet
34
Rev.1.0, 2004-02