HYB25D256161CE Datasheet, PDF (12/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Pin Configuration
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
15
13
A0-A12,
BA0, BA1
15
2
2
9
Column-Address
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 512x 32)
Sense Amplifiers
I/O Gating
DM Mask Logic
512
(x32)
Column
Decoder
8
COL0
1
32
32
32
Data
16
16
16
DQS
1
Generator
COL0
Write
FIFO
&
Drivers
clk clk
out in
Mask
2
32
Data
Input
Register
1
1
1
1
1
16
16
16
16
16
DQS
CK,
COL0
CK
2
DQ0-DQ15,
DM
LDQS, UDQS
Figure 2 Block Diagram (16 Mbit × 16)
Notes
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the
bidirectional DQ, UDQS and LDQS signals.
Datasheet
12
Rev.1.0, 2004-02