HYB25D256161CE Datasheet, PDF (59/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Timing Diagrams
5
Timing Diagrams
All Timing diagrams are based on DDR400 Time settings. For Time settings based on DDR500 see Table 18.
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Figure 34 Data Input (Write), Timing Burst Length = 4
Note:
1. DI n = Data In for column n.
2. 3 subsequent elements of data in are applied in programmed order following DI n.
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Figure 35 Data Output (Read), Timing Burst Length = 4
Note:
1. t_QH (Data output hold time from DQS)
2. t_DQSQ and t_QH are only shown once and are shown referenced to different edges of DQS, only for clarify of
illustration.
3. t_DQSQ and t_QH both apply to each of the four relevant edges of DQS.
4. t_DQSQ max. is used to determine the worst case setup time for controller data capture.
5. t_QH is used to determine the worst case hold time for controller data capture.
Datasheet
59
Rev.1.0, 2004-02