HYB25D256161CE Datasheet, PDF (60/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Timing Diagrams
Figure 36 Initialize and Mode Register Sets
Note:
1. * VTT is not applied directly to the device, however t_VTD must be greater than or equal to zero to avoid device
latchup.
2. ** t_MRD is required before any command can be applied and 200 cycles of CK are required before a Read
command can be applied.
3. The two Autorefresh commands may be moved to follow the first MRS, but precede the second Precharge All
command.
4. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
60
Rev.1.0, 2004-02