HYB25D256161CE Datasheet, PDF (56/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 18 Electrical Characteristics and AC Timing - Absolute Specifications –4/–5 ¹⁾ (cont’d)
Parameter
Symbol
–4
–5
Unit Note/Test Condition
DQS falling edge to CK setup time (write t_DSS
cycle)
DQS falling edge hold time from CK
t_DSH
(write cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
t_MRD
t_WPRES
t_WPST
t_WPRE
t_IS
t_IH
t_RPRE
t_RPST
t_RAS
t_RC
Auto-refresh to Active/Auto-refresh
t_RFC
command period
Active to Read delay
Active to Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
t_RCDRD
t_RCDWR
t_RP
t_RAP
t_RRD
Write recovery time
t_WR
Auto precharge write recovery +
t_DAL
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t_WTR
t_XSNR
t_XSRD
t_REFI
Min.
0.2
0.2
2
0
0.40
0.25
0.6
0.6
0.9
0.4
36
52
60
16
12
16
16
8
15
28
1
75
200
—
Max. Min.
—
0.2
—
0.2
—
2
—
0
0.60 0.40
—
0.25
—
0.6
—
0.6
1.1 0.9
0.6 0.4
70E+3 40
—
55
—
65
—
20
—
15
—
20
—
20
—
10
—
15
—
35
—
1
—
75
—
200
7.8 —
Max.
—
t_CK
—
t_CK
—
t_CK
—
ns
0.60 t_CK
—
t_CK
—
ns
—
ns
1.1
t_CK
0.6
t_CK
70E+3 ns
—
ns
—
ns
—
ns
—
—
ns
—
ns
—
ns
—
ns
—
t_CK
—
t_CK
—
ns
—
t_CK
7.8 µs
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1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
Datasheet
56
Rev.1.0, 2004-02