HYB25D256161CE Datasheet, PDF (16/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
3.2.4 Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with
bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register
Set command issued to reset the DLL should always be followed by a Mode Register Set command to select
normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
CK
CK
Command
DQS
DQ
Read
NOP
NOP
CL=3
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 3 Required CAS Latency
CAS Latency = 3, BL = 4
NOP
NOP
NOP
Don’t Care
Datasheet
16
Rev.1.0, 2004-02