HYB25D256161CE Datasheet, PDF (63/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Timing Diagrams
Figure 39 Self Refresh Mode
Note:
1. * = Device must be in the all banks idle state before entering Self Refresh Mode.
2. ** = t_XSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK) are
required before a Read command can be applied.
3. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
63
Rev.1.0, 2004-02