HYB25D256161CE Datasheet, PDF (57/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock
cycle time.
11) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 19 I_DD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; tRC = tRC,MIN;
DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; Refer to Chapter 4.4.1 for detailed test conditions.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE £ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS Å  VIH,,MIN, all banks idle; CKE Å  VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
IDD2Q
CS Å  VIHMIN, all banks idle; CKE Å  VIH,MIN;
address and other control inputs stable at Š VIH,MIN or £ VIL,MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current
one bank active; power-down mode; CKE £ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS Å  VIH,MIN; CKE Å  VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 3 ; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 3
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, distributed refresh
IDD5
Self-Refresh Current
CKE £ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; Refer to Chapter 4.4.1 for detailed test conditions.
IDD7
Datasheet
57
Rev.1.0, 2004-02