HYB25D256161CE Datasheet, PDF (23/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
CAS Latency = 3
Read
BAa, COL n
NOP
Read
BAa, COL b
CL=3
NOP
NOP
DOa-n
NOP
DOa-b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
When burst length = 4, the bursts are concatenated.
When burst length = 8, the second burst interrupts the first.
3 subsequent elements of data out appear in the programmed order following DO a-n.
3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 7 Consecutive Read Bursts (Burst Length = 4)
Don’t Care
CK
CK
Command
Address
DQS
DQ
CAS Latency = 3
Read
BAa, COL n
CL=3
Read
NOP
BAa, COL b
NOP
DO a-n
NOP
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 8 Non-Consecutive Read Bursts (Burst Length = 4)
Don’t Care
Datasheet
23
Rev.1.0, 2004-02