HYB25D256161CE Datasheet, PDF (66/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Timing Diagrams
Figure 42 Bank Read Access (Burst Length = 4)
Note:
1. DIS AP = disable Auto Precharge.
2. Don't care if A10 is High at this point.
3. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
4. NOP commands are shown for ease of illustration; other commands may be valid at these times.
5. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
66
Rev.1.0, 2004-02