HYB25D256161CE Datasheet, PDF (37/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
CK
CK
Command
Address
DQS
DQ
DM
Maximum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BA a, COL b
t_DQSS (max)
DI a-b
NOP
NOP
t_WR
PRE
BA (a or all)
t_RP
Minimum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BA a, COL b
t_DQSS (min)
DI a-b
NOP
NOP
t_WR
PRE
BA (a or all)
t_RP
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
t_WR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
Don’t Care
Figure 22 Write to Precharge: Non-Interrupting (Burst Length = 4)
Datasheet
37
Rev.1.0, 2004-02