HYB25D256161CE Datasheet, PDF (35/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
T1
T2
T3
T4
T5
T6
Write
NOP
BAa, COL b
t_DQSS (min)
DI a-b
NOP
NOP
Read
NOP
t_WTR
BAa, COL n
CL = 3
1
2
2
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
t_WTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
Figure 20 Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL3; BL8)
Datasheet
35
Rev.1.0, 2004-02