HYB25D256161CE Datasheet, PDF (26/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
CAS Latency = 3
Read
BAa, COL n
BST
NOP
CL=3
NOP
BAa, COL b
DOa-n
Write
NOP
t_DQSS (min)
DI a-b
DO a-n = data out from bank a, column n
.DI _{a-b = data in to bank a, column b}
1 subsequent elements of data out appear in the programmed order following DO a-n.
Data In elements are applied following Dl a-b in the programmed order, according to burst length.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 11 Read to Write (Burst Length = 4 or 8)
Don’t Care
CK
CK
Command
Address
DQS
DQ
CAS Latency = 3
Read
BA a, COL n
NOP
PRE
BA a or all
CL=3
NOP
NOP
t_RP
ACT
BA a, ROW
DOa-n
DO a-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 12 Read to Precharge (Burst Length = 4 or 8)
Don’t Care
Datasheet
26
Rev.1.0, 2004-02