HYB25D256161CE Datasheet, PDF (62/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Timing Diagrams
Figure 38 Auto Refresh Mode
Note:
1. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
3. DM, DQ, and DQS signals are all don't care/high-Z for operations shown.
4. The Timing reference is shown with respect to Vref-Crossing.
Datasheet
62
Rev.1.0, 2004-02