HYB25D256161CE Datasheet, PDF (58/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Electrical Characteristics
Table 20 I_DD Specification
Parameter
Symbol
–4
–5
Unit Note/ Test Condition ¹⁾
Typ. Max. Typ. Max.
Operating Current 0
I_DD0
–
Operating Current 1
I_DD1
–
Precharge Power-Down Standby Current I_DD2P –
Precharge Floating Standby Current
I_DD2F
–
Precharge Quiet Standby Current
I_DD2Q
–
Active Power-Down Standby Current
I_DD3P
–
Active Standby Current
I_DD3N
–
Operating Current Read
I_DD4R
–
Operating Current Write
I_DD4W
–
Auto-Refresh Current
I_DD5
–
Self-Refresh Current
I_DD6
–
Operating Current 7
I_DD7
–
115 75 90 mA ²⁾³⁾³⁾
135 95 110 mA ³⁾³⁾
6
45
mA ³⁾³⁾
45 30 36 mA ³⁾³⁾
35 20 28 mA ³⁾³⁾
23 13 18 mA ³⁾³⁾
65 43 54 mA ³⁾³⁾
150 100 120 mA ³⁾³⁾
160 100 130 mA ³⁾³⁾
240 140 190 mA ³⁾³⁾
2.8 1.4 2.8 mA ³⁾⁴⁾
315 210 250 mA ³⁾
1) Test conditions for typical values: V_DD = 2.6 V , T_A = 25 °C, test conditions for maximum values: V_DD = 2.7 V, T_A = 10 °C
2) I_DD specifications are tested after the device is properly initialized and measured at 200 MHz.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
4.4.1
I_DD Current Measurement Conditions
Legend: A = Activate, R = Read, RA = Read with Autoprecharge, P = Precharge, N = NOP or DESELECT
I_DD1: Operating Current: One Bank Operation
1. General test condition
a) Only one bank is accessed with t_RC,MIN.
b) Burst Mode, Address and Control inputs are changing once per NOP and DESELECT cycle.
c) 50% of data changing at every transfer
d) I_OUT = 0 mA.
2. Timing patterns
a) (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 11 × t_CK, t_RAS = 8 × t_CK
Setup:A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N -repeat the same timing with random address changing
I_DD7: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with t_RCMIN.
b) Burst Mode, Address and Control inputs on NOP edge are not changing.
c) 50% of data changing at every transfer
d) I_OUT = 0 mA.
2. Timing patterns
a) (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 *× t_CK, t_RAS = 8 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N
Read: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N - repeat the same timing with random address
Datasheet
58
Rev.1.0, 2004-02