HYB25D256161CE Datasheet, PDF (8/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

16M x 16 Double Data Rate Graphics DRAM
DDR SGRAM
HYB25D256161CE-5
HYB25D256161CE-4
1
Overview
1.1
Features
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8 µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
• V_DDQ = 2.6 V ± 0.1 V
• V_DD = 2.6 V ± 0.1 V
• P-TSOPII-66-1 package
• Lead- and halogene-free = green product
Table 1 Performance
Part Number Speed Code
max. Clock Frequency
@CL3
–4
–5
Unit
f_CK3
250
200
MHz
1.2
Description
The 16M x 16 Double Data Rate Graphics DRAM is a high-speed CMOS, dynamic random-access memory
containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 16M x 16 Double Data Rate Graphics DRAM uses a double-data-rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins. A single read or write access for the 16M x 16 Double Data
Rate Graphics DRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SGRAM during Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned with data for Writes.
The 16M x 16 Double Data Rate Graphics DRAM operates from a differential clock (CK and CK; the crossing of
CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control
signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output
data is referenced to both edges of DQS, as well as to both edges of CK.
Datasheet
8
Rev.1.0, 2004-02