HYB25D256161CE Datasheet, PDF (38/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
Maximum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
BA a, COL b
t_DQSS (max)
DI a-b
NOP
NOP
t_WR
PRE
BA (a or all)
2
3
3
1
1
NOP
t_RP
CK
CK
Command
Address
DQS
DQ
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
Write
BA a, COL b
NOP
NOP
t_DQSS (min)
NOP
t_WR
2
PRE
BA (a or all)
DI a-b
3
3
1
1
NOP
t_RP
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
t_WR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
Figure 23 Write to Precharge: Interrupting (Burst Length = 4 or 8)
Don’t Care
Datasheet
38
Rev.1.0, 2004-02