HYB25D256161CE Datasheet, PDF (24/72 Pages) Infineon Technologies AG – 16M x 16 Double Data Rate Graphics DRAM

HYB25D256161CE-[4/5]
256-Mbit Double Data Rate SGRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
CAS Latency = 3
Read
BAa, COL n
Read
Read
BAa, COL x
BAa, COL b
CL=3
Read
BAa, COL g
NOP
NOP
DOa-n DOa-n’ DOa-x DOa-x’ DOa-b
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 9 Random Read Accesses (Burst Length = 2, 4 or 8)
Don’t Care
Datasheet
24
Rev.1.0, 2004-02