HYB25D128323C Datasheet, PDF (9/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

128 Mbit DDR SGRAM
1
Overview
HYB25D128323C[-3/-3.3]
HYB25D128323C[-3.6/L3.6]
HYB25D128323C[-4.5/L4.5]
HYB25D128323C-5
1.1
Features
• Maximum clock frequency up to 333 MHz
• Maximum data rate up to 666 Mbps/pin
• Data transfer on both edges of clock
• Programmable CAS latency of 2, 3 and 4 clocks
• Programmable burst length of 2, 4 and 8
• Integrated DLL to align DQS and DQ transitions with CLK
• Data transfer signals are synchronized with byte wise bidirectional Data Strobe
• Data Strobe signal edge-aligned with data for Read operations
• Data Strobe signal center aligned with data for Write operations
• Differential clock inputs (CLK and CLK)
• Data mask for masking write data, one DM per byte
• Organization 1024K × 32 × 4 banks
• 4096 rows and 256 columns per bank
• 4K Refresh (32ms)
• Refresh Interval 7.8 µsec
• Autorefresh and Self Refresh available
• Standard JEDEC TF-XBGA 128 package
• Self-mirrored, symmetrical ball out
• Matched Impedance Mode interface (Z₀=60Ω)
• SSTL-2 JEDEC Weak Mode interface (Z₀=34Ω)
• IO voltage V_DDQ = 2.5 V
• V_DD power supply memory core:
– Speed sorts –3 and –3.3: 2.5 V < V_DD < 2.9 V
– Speed sorts L4.5, –4.5, and –5: V_DD = 2.5 V
– Speed sorts L3.6 and –3.6 support both V_DD modes
Table 1 Performance
Part Number Speed Code
CAS Latency 4
CAS Latency 3
Data Out Window
DQS-DQ Skew
t_CK4min.
f_CK4max.
t_CK3min.
f_CK3max.
t_QH
t_DQSQ
–3
–3.3 –3.6 –4.5 –5.0 L3.6 L4.5 Unit
3
3.3 3.6 4.5 5.0 3.6 4.5 ns
333 300 278 222 200 278 222 MHz
4.0 4.0 4.2 4.5 5.0 4.2 4.5 ns
250 250 238 222 200 238 222 MHz
1.05 1.15 1.26 1.58 1.75 1.26 1.58 ns
0.30 0.30 0.33 0.45 0.5 0.33 0.45 ns
1.2
Description
The Infineon 128Mbit DDR SGRAM is a ultra high performance graphics memory device, designed to meet all
requirements for high bandwidth intensive applications like PC graphics systems.
The 128Mbit DDR SGRAM uses a double-data-rate DRAM architecture organized as 4 banks × 4096 rows × 256
columns × 32 bits. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single Read or Write access to the DDR
Data Sheet
9
V1.7, 2003-07