HYB25D128323C Datasheet, PDF (15/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3
Register Set
3.1
Mode Register
The mode register stores the data for controlling the various operating modes of the DDR SGRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL ON and various vendor specific options. The default
value of the mode register is not defined. Therefore the mode register must be written after power up to operate
the DDR SGRAM. The DDR SGRAM should be activated with CKE already high prior to writing into the Mode
Register. The Mode Register is written by using the MRS command. The state of the address signals registered
in the same cycle as MRS command is written in the mode register. The value can be changed as long as all banks
are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS
latency (read latency from column address) uses A6.. A4. A7 is used for test mode, A8 is used for DLL Reset. A7,
A8 and BA1 must be set to low for normal DDR SGRAM operation. A9.. A11 is reserved for future use. BA0 selects
Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst
length, addressing modes and CAS latencies.
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
RFU RFU
RFU DLL
TM
CAS Latency
Extended Mode
Register Access
BA0 Accessed Register
0
Mode Register
1 Extend. Mode Reg.
Testmode
A7
mode
0
Normal
1
Testmode
BT
Burst Length
Burst Type
A3
Type
0
Sequential
1
Reserved
DLL Reset
A8
DLL Reset
0
No
1
Yes
CAS Latency
A6 A5 A4
Latency
010
2
011
3
100
4
All other Reserved
Mode Register
Figure 3 Mode Register Bitmap
Burst Length
A2 A1 A0
Length
Sequential Interleave
001
2
2
010
4
4
011
8
8
All other Reserved
Data Sheet
15
V1.7, 2003-07