HYB25D128323C Datasheet, PDF (43/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
1) T_A = 0 to 70 ° C; V_SS = 0 V
2) Under all conditions, V_DDQ must be less than or equal to V_DD
3) The speed sorts L3.6 and –3.6 support both V_DD modes: 2.5V ± 5% and 2.5V – 2.9V
4) V_DDQ = 2.5 V -/+5%
5) Typically the value of V_REF is expected to be 0.5 * V_DDQ of the transmitting device. V_REF is expected to track variations in
V_DDQ
6) Peak to peak AC noise on V_REF may not exceed 2% V_REF (DC)
7) V_TT of the transmitting device must track V_REF of the receiving device
8) Overshoots of V_IH must be limited to a voltage < (V_DDQ + 1.5 V) and a pulse width < 0.33 of the clock pulse
9) Undershoots of V_IL must be limited to a voltage > -1.5 V and a pulse width < 0.33 of the clock pulse
Table 15 AC Operation Conditions
Parameter
Symbol
Values
Unit Notes
min.
typ. max.
Input logic high voltage
V_IH
Input logic low voltage
V_IL
Clock Differential Input Voltage
V_ID
(CLK/CLK)
Clock Input Crossing Point (CLK/CLK)
I/O Reference Voltage
Input Slew Rate
V_IX
V_REF
r_I
V_REF + 0.50
V_REF + 0.60
V_REF + 0.50
V_SSQ - 0.3
V_SSQ - 0.3
V_SSQ - 0.3
1.2
1.0
1.2
1.0
V_REF - 0.2
0.49 × V_DDQ
1.0
—
—
—
—
—
—
—
—
—
—
V_REF
—
—
V_DDQ + 0.3
V_DDQ + 0.3
V_DDQ + 0.3
V_REF - 0.50
V_REF - 0.60
V_REF - 0.50
V_DDQ + 0.6
V_DDQ + 0.6
V_DDQ + 0.6
V_DDQ + 0.6
V_REF + 0.2
0.51 × V_DDQ
—
V
V
V
V
V
V
V
V
V
V
V
V
V/ns
L3.6, L4.5
–5.0
–3, –3.3, –3.6, –4.5
L3.6, L4.5
–5.0
–3, –3.3, –3.6, –4.5
L4.5
L3.6
–4.5, –5.0
–3, –3.3, –3.6, –4.5
—
—
—
DQ, DQS
+ Vtt = 0.5xV_DDQ
50 Ohm
Test point
15 pF
Figure 31 Output Test Circuit
Table 16 Pin Capacitances
Pin
A11.. A0, BA1, BA0, CKE, CS, CAS, RAS, WE
CLK, CLK
min.
1.0
1.0
Data Sheet
43
max.
2.5
2.5
Unit
pF
pF
V1.7, 2003-07