HYB25D128323C Datasheet, PDF (10/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Overview
SGRAM consists of a single 64-bit wide, one clock cycle data transfer at the internal DRAM core and two
corresponding 32-bit wide, one-half clock cycle data transfers at the I/O pins. The result is a data rate of 666 Mbits
/ sec per pin. The external data interface is 32 bit wide and achieves at 333 MHz system clock a peak bandwidth
of 2.66 Gigabytes/sec.
The device is supplied with 2.5 V resp. within the range of 2.5 V - 2.9 V for the memory core and 2.5 V for the
output drivers. Two drivers strengths are available: 2.5 V Matched Impedance Mode and SSTL2 Weak Mode. The
“Matched Impedance Mode” interface is optimized for high frequency digital data transfers and matches the
impedance of graphics board systems (60Ohm).
Auto Refresh and Self Refresh operations are both supported.
A standard JEDEC TF-XBGA 128 package is used which enables ultra high speed clock and data transfer rates.
The signals are mapped symmetrically to the balls in order to enable mirrored mounting in application.
The chip is fabricated in Infineon technologies advanced 256M process technology.
Data Sheet
10
V1.7, 2003-07