HYB25D128323C Datasheet, PDF (34/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.6.5 Write Interrupted by a Read
A Burst Write can be interrupted by a Read command sent to any bank. The DQs must be in the high impedance
state at least one clock cycle before the data of the interrupting read appears on the outputs to avoid data
contention. Before the Read Command is registered, any residual data from the burst write cycle must be masked
by DMx. Data that is presented on the DQ pins before the Read command is initiated, will actually be written to
the memory.
CLK
Command
DQSx
Write
NOP
NOP
Read
NOP
t_DQSS
Last valid
data
t_WTR
CL = 2
NOP
NOP
DQx
D-in D-in D-in D-in D-in D-in
0
1
2
3
4
5
D-out D-out
0
1
DMx
Data must be
masked
Data is masked
by Read
Burst length = 8
CL = 2
Figure 28 Write interrupted by Read
3.6.6 Write Interrupted by a Precharge
A Burst Write operation can be interrupted before completion of the burst by a Precharge of the same bank.
Random column access is allowed. A Write Recovery time (t_WR) is required from the last data to Precharge
command. When Precharge command is asserted, any residual data from the burst write cycle must be masked
by DMx.
Data Sheet
34
V1.7, 2003-07