HYB25D128323C Datasheet, PDF (40/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 12 Function Truth Table for CKE
Current
State
CKE CKE CS# RAS CAS
n-1 n
#
#
SELF
H
X
X
X
X
REFRESH _L
HHX
X
L
HL
HH
L
HL
HH
L
HL
HH
L
HL
L
L
L
L
X
X
X
POWER H
X
X
X
X
DOWN
L
HXX
X
L
L
X
X
X
ALL
H
H
X
X
X
BANKS
H
L
L
L
L
IDLE
H
L
H
X
X
H
L
L
H
H
H
L
L
H
H
H
L
L
H
L
H
L
L
L
X
L
X
X
X
X
All other H
H
X
X
X
states
WE#
X
X
H
X
X
X
X
X
X
X
X
H
X
H
L
X
X
X
X
Address Action
X
INVALID
X
Exit Self-Refresh ( Idle after t_SRX)
X
Exit Self-Refresh ( Idle after t_SRX)
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP ( Maintain Self Refresh)
X
INVALID
X
Exit Power Down ( Idle after t_PDEX)
X
NOP ( Maintain Power Down)
X
Refer to Function Truth Table
X
Enter Self Refresh
X
Enter Power-Down
X
Enter Power-Down
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
Refer to Power Down in this table
X
Refer to Funtion Truth Table
Notes
1)
1)
1)
1)
1)
1)
1)
2)
3)
2)
2)
2)
2)
2)
1) CKE low-to-high transition re-enables inputs asynchronously. A minimum setup time to CLK must be satisfied before any
commands other than EXIT are executed.
2) Power Down can be entered when all banks are idle (banks can be active or precharged)
3) Self Refresh can be entered only from the Precharge / Idle state.
Data Sheet
40
V1.7, 2003-07