HYB25D128323C Datasheet, PDF (28/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQSx
DQx
DMx
D-in D-in D-in D-in D-in D-in D-in D-in
0
1
2
3
4
5
6
7
Data is masked out
Burst length = 8
Figure 20 Data Mask Timing
3.5.14 Autoprecharge Operation
The Autoprecharge command is issued by setting column address A8 high when a Read or a Write command is
asserted to the DDR SGRAM. If A8 is low when Read or Write command is issued, a normal Read or Write burst
operation is executed and the bank remains active at the end of the burst sequence. When the Auto Precharge
command is activated, the active bank automatically begins to precharge at the earliest possible moment during
the Read or Write cycle after t_RAS(min.) is satisfied.
3.5.15 Read with Autoprecharge (READA)
If a Read with Auto-precharge command is initiated, the DDR SGRAM automatically enters the precharge
operation BL/2 clock cycles after the READA command and t_RAS(min.) is satisfied. If t_RAS(min.) has not been satisfied
yet, an internal interlock will delay the precharge operation until it is satisfied. Once the precharge operation has
started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (t_RP)
has been satisfied.
Data Sheet
28
V1.7, 2003-07