HYB25D128323C Datasheet, PDF (12/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Pin Configuration
Table 2 Signal and Pin Description
Pin
IO Type Detailed Function
CLK, CLK
Input
Clock: CLK and CLK# are differential clock inputs. All address and command inputs
are latched on the crossing of the positive edge of CLK and the negative edge of CLK.
Output data (DQ’s and DQS) is referenced to the crossing of CLK and CLK.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock,
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-
DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN
(row active in any bank). CKE is synchronous for POWER-DOWN entry and exit, and
for SELF REFRESH entry. CKE is asynchronous for SELF-REFRESH exit. CKE must
be maintained HIGH trough out READ and WRITE accesses. Input buffers (excluding
CLK, CLK) are disabled during POWER-DOWN. Input buffers (excluding CKE) are
disabled during SELF REFRESH. CKE is an SSTL2 input but will detect an LVCMOS
LOW level after VDD is applied.
CS
Input Chip Select: CS# enables the command decoder when low and disables it when high.
When the command decoder is disabled, new commands are ignored, but internal
operations continue. CS# is considered part of the command code.
RAS, CAS, WE Input
Command Inputs: CAS, RAS, and WE (along with CS) define the command to be
executed.
BA1, BA0
Input
Bank Address Inputs: BA0 and BA1 select to which internal bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. They also define which mode
register (mode register or extended mode register) is loaded during a MODE
REGISTER SET command.
A11.. A0
Input
Address Inputs: During a Bank Activate command cycle, A0-A11 defines the row
address (RA0-RA11). During a Read or Write command cycle, A0-A7 defines the
column address (CA0-CA7).
In addition to the column address, A8/AP is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A8 is high, the active bank is precharged.
If A8 is low, the Autoprecharge function is disabled.
During a Precharge command cycle, A8/AP is used to determine, which bank(s) will
be precharged. If A8/AP is high, all four banks will be precharged regardless of the
state of BA0 and BA1. If A8/AP is low, BA0 and BA1 define the bank to be precharged.
The address inputs also provide the op-code during a MODE REGISTER SET
command.
DQS3.. DQS0 I/O
DQ31.. DQ0 I/O
Data Strobes: The DQSx are the bidirectional strobe signals. At read cycles, the
DQSx signals are generated by the SGRAM and are edge-aligned to the data. At write
cycles, the DQS signals are generated by the controller. The rising or falling edge
indicates the center of the data valid window. Before and after a transfer cycle, DQSx
enters a preamble and a postamble state. The DQSx signals are mapped to the
following data bytes: DQS0 to DQ0.. DQ7, DQS1 to DQ8.. DQ15, DQS2 to
DQ16..DQ23, DQS3 to DQ24.. DQ31.
Data Input/Output: The DQx signals form the 32 bit wide data bus. At READ cycles
the pins are outputs and during WRITE cycles inputs. The data is transferred at both
edges of the DQSx signals.
Data Sheet
12
V1.7, 2003-07