HYB25D128323C Datasheet, PDF (26/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
CLK
DQSx
DQx
WRITE
NOP
t_DQSS
NOP
NOP
t_WPST
t_WPRES
t_WPREH
Data-in Data-in Data-in Data-in
0
1
2
3
Burst length = 4
Figure 18 Burst Write Operation
3.5.12 Burst Stop Command (BST)
A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop
Command has the fewest restrictions, making it the easiest method to terminate a burst operation before it has
been completed. When the Burst Stop Command is issued during a burst read cycle, read data and DQSx go to
a high impedance state after a delay which is equal to the CAS Latency set in the Mode Register. The Burst Stop
latency is equal to the CAS latency CL.The Burst Stop command is not supported during a write burst operation.
Burst Stop is also illegal during Read with Auto-Precharge.
Data Sheet
26
V1.7, 2003-07