HYB25D128323C Datasheet, PDF (24/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Clk
Command
PRE
NOP
NOP
CKE
Power Down
Mode entry
NOP
DESEL
Any
Command
Power Down
Mode exit
t_PDEX
NOP
DESEL
Figure 16 Power Down Mode timing
3.5.9 Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory
(read cycle). The burst length is programmable and set by address bits A0 - A3 during the Mode Register Setup
command. The burst length controls the number of words that will be output after a read command or the number
of words to be input after a write command. One word is 32 bits wide. The sequential burst length can be set to 2,
4 or 8 data words.
Table 6 Burst Mode and Sequence
Burst Length
Starting Column Address
A2
A1
A0
2
0
1
4
0
0
0
1
1
0
1
1
8
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Order of Access within a Burst
Type = Sequential
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
3.5.10 Burst Read Operation: (READ)
The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after t_RCD from
the bank activation. The address inputs (A7.. A0) determine the starting address for the burst. The burst length (2,
4 or 8) must be defined in the Mode Register. The first data after the READ command is available depending on
the CAS latency. The subsequent data is clocked out on the rising and falling edge of DQSx until the burst is
completed. The DQSx signal is generated by the DDR SGRAM during Burst Read Operations.
Data Sheet
24
V1.7, 2003-07