HYB25D128323C Datasheet, PDF (16/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.2
Extended Mode Register Setup (EMRS)
The Extended Mode Register is responsible for enabling / disabling the DLL in the HYB25D128323C and for
selecting the interface type for the IOs and input pins. The Extended Mode Register can be programmed by
performing a normal Mode Register Setup operation and setting the BA0 bit to high. All other bits of the EMRS
register are reserved and should be set to low.
The Bit A0 enables / disables the DLL.
The Bits A1 and A6 set the driver strength of the IOs. For detailed explanation, refer to the following table.
Table 3
A6
0
0
1
1
IO Driver Strength and Interface Settings
A1
Drive Strength Strength/
Impedance
0
SSTL-2 weak
60% / 34Ohm
1
SSTL-2 weak
60% / 34Ohm
0
RFU
RFU
1
matched
30% / 60Ohm
impedance mode
IO Power Supply
VDDQ
2.5V
2.5V
RFU
2.5V
Comment
replacement for strong mode
–
Do not use
output driver matches line
impedance
Note: The combination A6=0 and A1=0 defines SSTL-2 strong mode in 32M DDR SGRAM which is not supported
in this device.
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
1
RFU must be set to "0"
DS1
RFU must be set to "0"
DS0 DLL
Extended Mode Register
Extended Mode
Register Access
BA0 Accessed Register
0
Mode Register
1 Extend. Mode Reg.
A6
A1
Drive Strength
0
0
SSTL II-Weak Mode
0
1
SSTL II-Weak Mode
1
0
RFU
1
1 Matched Impedance 2.5V
A0
DLL Enable
0
Enable
1
Disable
Figure 4 Extended Mode Register Bitmap
3.3
Signal and Timing Description
3.3.1 General Description
The 128Mbit DDR SGRAM is a 16MByte Synchronous Graphics DRAM. It consists of four banks. Each bank is
organized as 4096 rows × 256 columns × 32 bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate command, which
is then followed by a Read or Write command. The address bits registered coincident with the Activate command
are used to select the bank and the row to be accessed. BA1 and BA0 select the bank, address bits A11.. A0 select
the row. Address bits A7.. A0 registered coincident with the Read or Write command are used to select the starting
column location for the burst access.
The regular Single Data Rate SGRAM read and write cycles only use the rising edge of the external clock input.
For the DDR SGRAM, the special signals DQSx (Data Strobe) are used to mark the data valid window. During
Data Sheet
16
V1.7, 2003-07