HYB25D128323C Datasheet, PDF (14/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Pin Configuration
Column Addresses A7-A0, AP
Column Address Buffer
Column Address Counter
Row Addresses A11-A0, BA1-BA0
Row Address Buffer
Row Decoder
Memory
Array
Bank 0
4096 x 256
x 32 bit
Row Decoder
Memory
Array
Bank 1
4096 x 256
x 32 bit
Row Decoder
Memory
Array
Bank 2
4096 x 256
x 32 bit
Row Decoder
Memory
Array
Bank 3
4096 x 256
x 32 bit
Input Buffers
Output Buffers
DQ31-DQ24 DQ23-DQ16 DQ15-DQ8 DQ7-DQ0
Figure 2 Functional blocks
CLK
CLK#
CKE
CS#
RAS#
CAS#
WE#
V_ref
Data Sheet
14
V1.7, 2003-07