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HYB25D128323C Datasheet, PDF (39/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM
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HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 11 Function Truth Table I (cont’d)
Current State Command
Address
WRITE
RECOVERING
with Auto-
precharge
DESEL
NOP
BST
READ / READA
X
X
X
BA, CA, A8
WRITE / WRITEA BA, CA, A8
ACT
BA, RA
PRE / PREAL
BA ,A8
AREF / SREF
X
MRS / EMRS
OP-Code
REFRESH
DESEL
X
NOP
X
BST
X
READ / READA BA, CA, A8
WRITE / WRITEA BA, CA, A8
ACT
BA, RA
PRE / PREAL
BA ,A8
AREF / SREF
X
MRS / EMRS
OP-Code
(EXTENDED DESEL
X
MODE
REGISTER
NOP
X
SET)
BST
X
READ / READA BA, CA, A8
WRITE / WRITEA BA, CA, A8
ACT
BA, RA
PRE / PREAL
BA ,A8
AREF / SREF
X
MRS / EMRS
OP-Code
Action
NOP (Precharge after tWR)
NOP (Precharge after tWR)
NOP (Precharge after tWR)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Idle after tRC)
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Idle after two clocks)
NOP (Idle after two clocks)
NOP (Idle after two clocks)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
1), 2)
1)
1)
1)
11)
1) Illegal to bank specified states; function may be legal in the bank indicated by BAx, depending on the state of that bank
2) Must satisfy bus contention, bus turn around, write recovery requirements.
3) If both banks are idle, and CKE is inactive, the device will enter Power Down Mode. All input buffers except CKE, CLK and
CLK# will be disabled.
4) If both banks are idle, and CKE is deactivated coincidentally with an AutoRefresh command, the device will enter
SelfRefresh Mode. All input buffers except CKE will be disabled.
5) Illegal, if tRRD is not satisfied.
6) Illegal, if tRAS is not satisfied.
7) Must satisfy burst interrupt condition.
8) Must mask two preceding data bits with the DM pin.
9) Illegal, if tRCD is not satisfied.
10) Illegal, if tWR is not satisfied.
11) Illegal, if tRC is not satisfied.
Note: All entries assume the CKE was High during the preceding clock cycle
Data Sheet
39
V1.7, 2003-07
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