HYB25D128323C Datasheet, PDF (22/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

Table 5
A8/AP
0
0
0
0
1
Precharge Control
BA1
0
0
1
1
X
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
BA0
0
1
0
1
X
Precharged
Bank A Only
Bank B Only
Bank C Only
Bank D Only
All Banks
Clk
Command ACT
NOP
PRE
NOP
ACT
Addresses
Bank A
Row Add
t_RAS
Bank A
t_RC
Bank A
Row Add
t_RP
Figure 13 Precharge Command Timing
3.5.6 Self Refresh
The self refresh mode can be used to retain the data in the DDR SGRAM if the chip is powered down. To set the
DDR SGRAM into a self refreshing mode, a Self Refresh command must be issued and CKE held low at the rising
edge of the clock. Once the self Refresh command is initiated, CKE must stay low to keep the device in Self
Refresh mode. During the Self refresh mode, all of the external control signals are disabled except CKE. The clock
is internally disabled during Self Refresh operation to reduce power. An internal timing generator guarantees the
self refreshing of the memory content. To exit the Self Refresh mode, a stable external clock is needed for the DLL
before returning CKE high. After the Power Down Exit time(t_PDEX), a Deselect or NOP command is issued and CKE
is held high for longer than t_SREX in order to lock the DLL.
Data Sheet
22
V1.7, 2003-07