HYB25D128323C Datasheet, PDF (46/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 17 Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 (cont’d)
Part Number Extension
–3
–3.3
–3.6
–4.5
–5
Unit Note¹⁾
Interface
MIM
MIM
MIM
WM/MIM WM/MIM — ²⁾
Parameter
Symbol min. max. min. max. min. max. min. max. min. max. — —
Internal WRITE to t_WTR
READ command
delay
1 —1 —1
— 1 — 1 — t_CK —
Write DQS High
level Width
t_DQSH 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 t_CK —
Write DQS Low level t_DQSL
Width
0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 0.35 0.65 t_CK —
Refresh Cycle
Refresh Period
(4096 cycles)
Average periodic
refresh interval
Refresh to Refresh
command interval
t_REF
t_REFC
t_REFC
— 32 — 32 — 32 — 32 — 32 ms —
— 7.8 — 7.8 — 7.8 — 7.8 — 7.8 us —
— 15.7 — 15.7 — 15.7 — 15.7 — 15.7 µs —
Mode Setup, Power Down & Self Refresh
Mode Register Set t_MRD
cycle time
2 —2 —2
— 2 — 2 — t_CK —
Self Refresh Exit
time
t_SREX
200 —
200 —
200 —
200 —
200 —
t_CK —
Power Down Exit
time
t_PDEX
2*t_CK —
+ t_IS
2*t_CK —
+ t_IS
2*t_CK —
+ t_IS
1*t_CK —
+ t_IS
1*t_CK —
+ t_IS
ns —
1) All parameters only valid for: T_A = 0 to 70 °C; V_SS = 0 V; 2.5 V < V_DD < 2.9 V for –3 and –3.3; 2.375 V < V_DD < 2.9 V for
–3.6; V_DD = 2.5 V ± 0.125 V for –4.5 and –5; V_DDQ = 2.5 V ± 0.125 V
2) Maximum clock rate is only guaranteed with the specified interface. The SSTL2-Weak Mode interface is limited to a
maximum speed of 250MHz.
3) The Write Recovery Time starts at the first rising edge of clock after the last valid (falling) DQS edge of the slowest DQS
signal.
Table 18 Timing Parameters for speed sorts L3.6 and L4.5
Part Number Extension
L3.6
Interface
MIM
Parameter
Symbol min.
max.
L4.5
WM/MIM
min. max.
Unit
—
—
Note ¹⁾
2)
—
Clock and Clock Enable
Clock Cycle Time
System frequency
Clock high level width
Data Sheet
3.6
6.0 4.5
6.0 ns CL = 4
t_CK
4.2
10 4.5
10 ns CL = 3
f_CK
166
278 166
222 MHz CL = 4
f_CK
100
238 100
222 MHz CL = 3
t_CH
0.45
0.55 0.45
0.55 t_CK —
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V1.7, 2003-07