HYB25D128323C Datasheet, PDF (45/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 17 Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 (cont’d)
Part Number Extension
–3
–3.3
–3.6
–4.5
–5
Unit Note¹⁾
Interface
MIM
MIM
MIM
WM/MIM WM/MIM — ²⁾
Parameter
Symbol min. max. min. max. min. max. min. max. min. max. — —
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time t_AC
from Clock
-0.5 +0.5 -0.5 +0.5 -0.55 +0.55 -0.7 +0.7 -0.7 +0.7 ns —
DQS edge to Clock t_DQSCK -0.5 +0.5 -0.5 +0.5 -0.55 +0.55 -0.7 +0.7 -0.7 +0.7 ns —
edge skew
DQS Read
Preamble
t_RPRE 0.7 0.9 0.7 0.9 0.7 0.9 0.7 0.9 0.7 0.9 t_CK —
DQS Read
Postamble
t_RPST 0.8 1.1 0.8 1.1 0.8 1.1 0.8 1.1 0.8 1.1 t_CK —
Row to Column
Delay Time for
Reads
t_RCDDC 4
—4
—4
—
4
—
4
—
t_CK —
DQS edge to output t_DQSQ
data edge skew
— +0.3 — +0.3 —
+0.33 — +0.45 — +0.5 ns —
Data hold skew
factor
t_QHS
— 0.33 — 0.33 — 0.36 — 0.45 — 0.5 ns —
Data Output Hold t_QH
time from DQS
t_HP-t_QHS
t_HP-t_QHS
t_HP-t_QHS
t_HP-t_QHS
t_HP-t_QHS
ns —
Write Cycle Timing Parameters for Data and Data Strobe
Row to Column
Delay Time for
Writes
t_RCDWR 2
—
Clock to rising Edge t_DQSS
DQS (Write Latency)
0.75 1.1
Data-in to DQS
Setup Time
t_QDQSS 0.40 —
Data-in to DQS Hold t_QDQSH 0.40 —
Time
Data Mask to DQS t_DMDQSS 0.40 —
Setup Time
Data Mask to DQS t_DMDQSH 0.40 —
Hold Time
Clock to DQS Write t_WPRES 0 —
Preamb. Setup Time
Clock to DQS Write t_WPREH 0.25 —
Preamble Hold Time
DQS Write
Postamble Hold
Time
t_WPST 0.4 0.6
Write Recovery
t_WR
2—
Time
2—
0.75 1.1
0.40 —
0.40 —
0.40 —
0.40 —
0—
0.25 —
0.4 0.6
2—
2—
0.75 1.1
0.40 —
0.40 —
0.40 —
0.40 —
0—
0.25 —
0.4 0.6
2—
2 — 2 — t_CK —
0.75 1.25 0.75 1.25 t_CK —
0.6 — 0.6 — ns —
0.6 — 0.6 — ns —
0.6 — 0.6 — ns —
0.6 — 0.6 — ns —
0 — 0 — t_CK —
0.25 — 0.25 — t_CK —
0.4 0.6 0.4 0.6 t_CK —
2
—
2
—
t_CK ³⁾
Data Sheet
45
V1.7, 2003-07