HYB25D128323C Datasheet, PDF (18/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Table 4 Mapping of DQSx and DMx
data strobe signal
data mask signal
Controlled data bus
DQS0
DQS1
DQS2
DQS3
DM0
DM1
DM2
DM3
DQ7 .. DQ0
DQ8 .. DQ15
DQ16 .. DQ23
DQ24 .. DQ31
The minimum time during which the output data is valid is critical for the receiving device. This also applies to the
Data Strobe DQS during a read since it is tightly coupled to the output data. The parameters t_QH and t_DQSQ define
the minimum output data valid window.
Prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit
from Hi-Z to a valid logic low. This is referred to as the data strobe “read preamble” t_RPRE.
Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe
signals transit from a valid logic low to Hi-Z. This is referred to as the data strobe “read postamble” t_RPST.
T0
t_CH
CLK,
CLK#
DQS
DQx
T1
t_CL
T2
T3
t_CK
t_HP
t_DQSCK
"Preamble"
t_RPRE
t_AC
D
t_QH
t_DQSQ
D+1
t_QHS
D+2
T4
VIH
VIL
"Postamble"
t_RPST
VIH
VTT
VIL
VIH
D+3
VTT
VIL
Figure 6 DQS Timing for Read
3.4.3.2 Operation at Burst Write
During a write burst, control of the data strobe is driven by the memory controller. The DQSx signals are nominally
centered with respect to data and data mask. The tolerance of the data and data mask edges versus the data
strobe edges during writes are specified by the setup and hold time parameters of data (t_QDQSS & t_QDQSH) and data
mask (t_DMDQSS & t_DMDQSH). The input data is masked in the same cycle when the corresponding DMx signal is high
(i.e. the DMx mask to write latency is zero.)
Data Sheet
18
V1.7, 2003-07