HYB25D128323C Datasheet, PDF (50/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Table 24 HYB25D128323CL3.6
Frequency / t_CK
278 MHz / 3.6 ns
CAS latency
4
250 MHz / 4.0 ns 4
222 MHz / 4.5 ns 3
200 MHz / 5.0 ns 3
166 MHz / 6.0 ns 3
t_RC t_RFC t_RAS t_RP t_WR t_RRD t_DAL t_RCDRD
13 15 9 4 2 3 6 4
t_RCDWR
2
Units
t_CK
13 15 9 4 2 3 6 4
2
t_CK
12 14 8 4 2 2 6 4
2
t_CK
10 12 7 3 2 2 5 3
2
t_CK
9 11 6 3 2 2 5 3
2
t_CK
Table 25 HYB25D128323CL4.5
Frequency / t_CK
222 MHz / 4.5 ns
CAS latency
3
200 MHz / 5.0 ns 3
183 MHz / 5.5 ns 3
166 MHz / 6.0 ns 3
143 MHz / 7.0 ns 3
t_RC t_RFC t_RAS t_RP t_WR t_RRD t_DAL t_RCDRD
12 14 8 4 2 2 6 4
t_RCDWR
2
Units
t_CK
12 14 8 4 2 2 6 4
2
t_CK
12 14 8 4 2 2 6 4
2
t_CK
10 12 7 3 2 2 5 3
2
t_CK
9 11 6 3 2 2 5 3
2
t_CK
Table 26 Operating Currents
Parameter & Test Condition
Symbol
OPERATING CURRENT: One bank; I_DD0
Active-Precharge; t_RC = t_RC(min.);
t_CK = t_CK(min.); DQ, DM and DQS inputs
changing once per clock cycle;
Address and control inputs changing
once every two clock cycles
OPERATING CURRENT: One bank; I_DD1
Active-Read-Precharge; BL=4; CL=4;
t_RCDDC = 4*t_CK; t_RC = t_RC(min.);
t_CK = t_CK(min.); I_OUT = 0mA; Address and
control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN
STANDBY CURRENT: All banks idle;
power-down mode; t_CK = t_CK(min.);
CKE=LOW
I_DD2P
–3 –3.3 –3.6 –4.5 –5.0 L3.6 L4.5 Unit Notes
max.
typ. typ.
200 190 180 160 150
mA ¹⁾
230 220 110 190 180
mA
26 22 22 14 14 10 7 mA
Data Sheet
50
V1.7, 2003-07