HYB25D128323C Datasheet, PDF (30/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Burst length = 4
CAS latency = 3
T0
T1
T2
T3
CLK
Command
BANK A
ACTIVATE
NOP
NOP
t RCD(min)
t RAS(min)
READ A
+ AP
T4
NOP
BL / 2
DQSx
DQx
CL = 3
T5
T6
T7
T8
NOP
NOP
NOP
NOP
t RP
Begin of
Auto Precharge
D-out D-out D-out D-out
0
1
2
3
Figure 22 Read Concurrent Auto Precharge
Table 7 Concurrent Read Auto Precharge Support
Asserted
For same Bank
Command
T4
T5
T6
READ
NO
NO
NO
READ+AP
YES
YES
NO
ACTIVATE
NO
NO
NO
PRECHARGE YES
YES
NO
For different Bank
T4
T5
NO
YES
NO
YES
YES
YES
YES
YES
T6
YES
YES
YES
YES
Note: This table is for the case of Burst Length = 4, CAS Latency =3 and t_WR=2 clocks
When READ with Auto Precharge is asserted, new commands can be asserted at T4,T5 and T6 as shown in
Table 7.
An Interrupt of a running READ burst with Auto Precharge i.e. at T4 and T5 to the same bank with another
READ+AP command is allowed, it will extend the begin of the internal Precharge operation to the last READ+AP
command.
Interrupts of a running READ burst with Auto Precharge i.e. at T4 are not allowed when doing concurrent
command to another active bank. ACTIVATE or PRECHARGE commands to another bank are always possible
while a READ with Auto Precharge operation is in progress.
3.5.16 Write with Autoprecharge (WRITEA)
If A8 is high when a Write command is issued, the Write with Auto-Precharge function is performed. The internal
precharge begins after the write recovery time t_WR and t_RAS(min.) are satisfied.
If a Write with Auto Precharge command is initiated, the DDR SGRAM automatically enters the precharge
operation at the first rising edge of CLK after the last valid edge of DQS (completion of the burst) plus the write
recovery time t_WR. Once the precharge operation has started, the bank cannot be reactivated and the new
command can not be asserted until the Precharge time (t_RP) has been satisfied. If t_RAS(min.) has not been satisfied
yet, an internal interlock will delay the precharge operation until it is satisfied.
Data Sheet
30
V1.7, 2003-07