HYB25D128323C Datasheet, PDF (19/53 Pages) Infineon Technologies AG – 128 Mbit DDR SGRAM

HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
DQSx
DMx
DQx
t_DMDQSS
t_DMDQSS
t_DMDQSH
t_QDQSH
t_QDQSH
Q
t_QDQSS
Q+1
Q+2
t_QDQSS
Input Data masked
Q+3
t_DMDQSH
Q+4
VIH
VTT
VIL
VIH
VTT
VIL
VIH
VTT
VIL
Figure 7 DQS and DM Timing at Write
Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal
(DQSx) transits from Hi-Z to a valid logic low. This is referred to as the data strobe “Write Preamble”. Once the
burst of write data is concluded, given that no subsequent burst write operation is initiated, the data strobe signal
(DQSx) transits from a valid logic low to Hi-Z. This is referred to as the data strobe “Write Postamble”, t_WPST. For
DDR SGRAM, data is written with a delay which is defined by the parameter t_DQSS (DDR write latency). This is
different than the single data rate SGRAM where data is written in the same cycle as the Write command is issued.
CLK,
CLK#
DQSx
DQx
WR
t_DQSS
t_WPREH
"Preamble"
t_WPRES
t_WPST
"Postamble"
Q
Q+1
Q+2
Q+3
VIH
VIL
VIH
VTT
VIL
VIH
VTT
VIL
Figure 8 DQS Pre/Postamble at Write
Data Sheet
19
V1.7, 2003-07