TLE94106EL Datasheet, PDF (63/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
7.7.1 Status register definition
SYS_DIAG1
Global status 1 (Address Byte [OP]001 10[LABT]1_B)
D7
D6
D5
D4
SPI_ERR
LE
rc
r
VS_UV
rc
VS_OV
rc
D3
NPOR
rc
D2
D1
TSD
TPW
r
rc
rc
D0
reserved
r
Field
Bits
SPI_ERR D7
LE
D6
VS_UV
D5
VS_OV
D4
NPOR
D3
TSD
D2
TPW
D1
reserved D0
Type
rc
r
rc
rc
rc
rc
rc
r
Description
SPI error detection
0_B No SPI protocol error is detected (default value).
1_B An SPI protocol error is detected.
Load error detection (logic OR combination of Open Load and
Overcurrent)
0_B No Open Load and no Overcurrent detected (default value)
1_B Open Load or Overcurrent detected in at least one of the
power outputs. Error latched. Faulty output is latched off in
case of Overcurrent
VS Undervoltage error detection
0_B No undervoltage on V_S detected (default value)
1_B Undervoltage on V_S detected. Error latched and all outputs
disabled.
VS Overvoltage error detection
0_B No overvoltage on V_S detected (default value)
1_B Overvoltage on V_S detected. Error latched and all outputs
disabled.
Not Power On Reset (NPOR) detection
0_B POR on EN or VDD supply rail (default value)
1_B No POR
Temperature shutdown error detection
0_B Junction temperature below temperature shutdown
threshold (default value)
1_B Junction temperature has reached temperature shutdown
threshold. Error latched and all outputs disabled.
Temperature pre-warning error detection
0_B Junction temperature below temperature pre-warning
threshold (default value)
1_B Junction temperature has reached temperature pre-warning
threshold.
Bit reserved. Always reads ‘0’.
Note:
The LE bit in the Global Status register is read only. It reflects an OR combination of the respective
open load and overcurrent errors of the half-bridge channels. If all OC/ OL bits of the respective high-
side and low-side channels are cleared to ‘0’, the LE bit will be automatically updated to ‘0’.
Data Sheet
63
1.0
2016-09-08