TLE94106EL Datasheet, PDF (36/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Half-Bridge Outputs
Table 9
Control and Status register bit state in the event of an overtemperature condition for an
activated power switch
REGISTER REGISTER NAME Bit
TYPE
T_j < T_jW
Bit State
T_j > T_jW
Bit State
T_j > T_jSD
Bit State
T_j < T_jSD - T_jHYS
Bit State
Control HB_ACT_CTRL_n HBn_HS_EN 1
1
1
‘1’ (outputs
HBn_LS_EN
(all outputs are latched off
are latched unless error is
off)
cleared)
Status
SYS_DIAG_1: Global TPW
0
status 1
Status
SYS_DIAG_1: Global TSD
0
status 1
1
(latched)
0
1
(latched)
1
(latched)
‘0’ if error is
cleared and
T_j < T_jW , else ‘1’
‘0’ if error is
cleared, else
‘1’
6.2.4 Overvoltage and undervoltage shutdown
The power supply rails V_S and V_DD are monitored for supply fluctuations. The V_S supply is monitored for under-
and over-voltage conditions where as the V_DD supply is monitored for under-voltage conditions.
6.2.4.1 V_S Undervoltage
In the event the supply voltage V_S drops below the switch off voltage V_{UV OFF}, all output stages are switched off,
however, the logic information remains intact and uncorrupted. The V_S under-voltage error bit, VS_UV,
located in SYS_DIAG_1: Global Status 1 status register, will be set and latched. If V_S rises again and reaches the
switch on voltage V_{UV ON} threshold, the power stages will automatically be activated. The VS_UV error bit
should be cleared to verify if the supply disruption is still present. See Figure 12.
6.2.4.2 V_S Overvoltage
In the event the supply voltage V_S rises above the switch off voltage V_{OV OFF}, all output stages are switched off.
The V_S over-voltage error bit, VS_OV, located in SYS_DIAG_1: Global Status 1 status register, will be set and
latched. If V_S falls again and reaches the switch on voltage V_{OV ON} threshold, the power stages will automatically
be activated. The VS_OV error bit should be cleared to verify if the overvoltage condition is still present. See
Figure 12.
6.2.4.3 V_DD Undervoltage
In the event the VDD logic supply decreases below the undervoltage threshold, V_{DD POffR}, the SPI interface shall
no longer be functional and the TLE94106EL will enter reset.
The digital block will be initialized and the output stages are switched off to High impedance. The
undervoltage reset is released once V_DD voltage levels are above the undervoltage threshold, V_{DD POR}.
The reset event is reported in SYS_DIAG1 by the NPOR bit (NPOR = 0) once the TLE94106EL is in normal mode
(EN = High ; VDD > V_{DD POR}).
Data Sheet
36
1.0
2016-09-08