TLE94106EL Datasheet, PDF (47/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
SCLK
0
CSN
MO = SDI1
0
SDI2 = SDO1
GEF1
HiZ
HiZ
GEF1
SDI3 = SDO2 _OR
GEF1/2
MI = SDO3
OR
GEF1/2/3
HiZ
OR
HiZ
GEF1/2
HiZ
OR
HiZ
GEF1/2/3
Time
Figure 22 Global Error Flag with zero SCLK clock cycle in daisy chain consisting only of TLE941xy
devices
Note:
Some SPI protocol errors such as the LSB of an address byte is wrongly equal to 0, may be reported
in the SPI_ERR bit of another device in the daisy chain (refer to Chapter 7.1.3 and Chapter 7.7 for
more details on SPI_ERR). In this case some devices might accept wrong data during the corrupted
SPI frame. Therefore if one of the devices in the daisy chain reports an SPI error, it is recommended
to verify the content of the registers of all devices.
7.4
Status register change during SPI communication
If a new failure occurs after the transfer of the data byte(s), i.e. between the end of the last address byte and
the CSN rising edge, this failure will be reported in the next SPI frame (see example in Figure 23).
SCLK
0
8 CLOCK CYCLES 8 CLOCK CYLES
8 CLOCK CYCLES 8 CLOCK CYLES
CSN
End of the New failure
address byte detection
SDI
SDO
0
ADDRESS BYTE
DATA BYTE
Failure is NOT notified in this SPI frame
GEF GLOBAL STATUS
DATA BYTE
Read status byte
corresponding to the failure
ADDRESS BYTE
DATA BYTE
Failure notified in the new SPI frame
HiZ
HiZ
GEF GLOBAL STATUS
DATA BYTE
Time
Figure 23 Status register change during transfer of data byte - Example in independent slave
configuration
Data Sheet
47
1.0
2016-09-08