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TLE94106EL Datasheet, PDF (16/75 Pages) Infineon Technologies AG – Six half bridge power outputs
TLE94106EL
General Product Characteristics
Table 5
Electrical Characteristics, VS =5.5 V to 18 V, VDD = 3.0V to 5.5V, Tj = -40°C to +150°C, EN= HIGH,
IOUTn= 0 A; Typical values refer to VDD = 5.0 V, VS = 13.5 V and TJ = 25 °C unless otherwise
specified; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified) (cont’d)
Parameter
Symbol
Values
Unit Note or
Min. Typ. Max.
Test Condition
Number
L-output voltage level
Tri-state Leakage Current
VSDOL
ISDOLK
–
0.2 0.4 V
-1 – 1
µA
Tri-state input capacitance
CSDO
–
10
Data Input Timing. See Figure 15 and Figure 17.
SCLK Period
SCLK High Time
tpCLK
tSCLKH
SCLK Low Time
tSCLKL
SCLK Low before CSN Low
CSN Setup Time
SCLK Setup Time
SCLK Low after CSN High
SDI Setup Time
SDI Hold Time
Input Signal Rise Time at pin
SDI, SCLK, CSN
tBEF
tlead
tlag
tBEH
tSDI_setup
tSDI_hold
trIN
200 –
0.45 * –
tpCLK
0.45 * –
tpCLK
125 –
250 –
250 –
125 –
30 –
30 –
–
–
Input Signal Fall Time at pin SDI, tfIN
SCLK, CSN
–
–
Delay time from EN falling edge tDMODE
–
–
to standby mode
Minimum CSN High Time
tCSNH
Data Output Timing. See Figure 15.
5
–
SDO Rise Time
SDO Fall Time
SDO Enable Time after CSN
falling edge
trSDO
tfSDO
tENSDO
–
30
–
30
–
–
SDO Disable Time after CSN tDISSDO
–
–
rising edge
Duty cycle of incoming clock at dutySCLK 45 –
SCLK
15 pF
–
ns
0.55 * ns
tpCLK
0.55 * ns
tpCLK
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
50 ns
50 ns
8
µs
–
µs
80 ns
80 ns
75 ns
75 ns
55 %
ISDOL = 1.6 mA
VCSN = VDD;
0V < VSDO < VDD
3)
P_4.4.57
P_4.4.58
P_4.4.59
3)
P_4.4.60
3)
P_4.4.61
3)
P_4.4.62
3)
P_4.4.63
3)
P_4.4.64
3)
P_4.4.65
3)
P_4.4.66
3)
P_4.4.67
3)
P_4.4.68
3)
P_4.4.69
3)
P_4.4.70
3)
P_4.4.71
3)
P_4.4.72
Cload = 40pF 3)
Cload = 40pF 3)
Low Impedance 3)
P_4.4.73
P_4.4.74
P_4.4.75
High Impedance 3) P_4.4.76
3)
P_4.4.77
SDO Valid Time for VDD = 3.3V tVASDO3
–
70 95
ns
VSDO < 0.2 x VDD
P_4.4.78
VSDO > 0.8 x VDD
Cload = 40pF 3)
Data Sheet
16
1.0
2016-09-08