TLE94106EL Datasheet, PDF (38/75 Pages) Infineon Technologies AG – Six half bridge power outputs

TLE94106EL
Serial Peripheral Interface (SPI)
7
Serial Peripheral Interface (SPI)
The TLE94106EL has a 16-bit SPI interface for output control and diagnostics. This section describes the SPI
protocol, the control and status registers.
7.1
SPI Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input
SCLK provided by the microcontroller. SCLK must be Low during CSN falling edge (Clock Polarity = 0). The SPI
incorporates an in-frame response: the content of the addressed register is shifted out at SDO within the same
SPI frame (see Figure 19 and Figure 21).The transmission cycle begins when the chip is selected by the input
CSN (Chip Select Not), Low active. After the CSN input returns from Low to High, the word that has been read
is interpreted according to the content. The SDO output switches to tri-state status (High impedance) at this
point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input register with every
falling edge on SCLK. The state of SDO is shifted out of the output register at every rising edge on SCLK (Clock
Phase = 1). The SPI protocol of the TLE94106EL is compatible with independent slave configuration and with
daisy chain. Daisy chaining is applicable to SPI devices with the same protocol.
Writing, clearing and reading is done byte wise. The SPI configuration and status bits are not cleared
automatically by the device and therefore must be cleared by the microcontroller, e.g. if the TSD bit was set
due to over temperature (refer to the respective register description for detailed information).
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
SCLK
SDI
SDO
time
CSN low to high: data from shift register is transferred to output functions
LSB
Actual data
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SDI: will accept data on the falling edge of SCLK signal
Actual status
GEF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SDO will change state on the rising edge of SCLK signal
time
New data
01
++
time
New status
GEF 0 1
+ ++
time
Figure 13 SPI Data Transfer Timing (note the reversed order of LSB and MSB as shown in this figure
compared to the register description)
SPI messages are only recognized if a minimum set time, tSET, is observed upon rising edge of the EN pin
(Figure 14).
Data Sheet
38
1.0
2016-09-08